SPARC T5

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SPARC T5

Oracle SPARC T5
General information
Launched	2013
Discontinued	2017
Performance
Max. CPU clock rate	3.6 GHz
Cache
L1 cache	16×(16+16) KB
L2 cache	16×128 KB
L3 cache	8 MB
Architecture and classification
Technology node	28 nm
Instruction set	SPARC V9
Physical specifications
Cores	16
Products, models, variants
Core name	S3
History
Predecessor	SPARC T4
Successor	SPARC M7

SPARC T5 is the fifth generation multicore microprocessor of Oracle's SPARC T series family.^[1] It was first presented at Hot Chips 24 in August 2012,^[2] and was officially introduced with the Oracle SPARC T5 servers in March 2013.^[3] The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.^[4]

The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz.^[5] The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution,^[6] incorporates one floating point unit, one dedicated cryptographic unit per core.^[7]

The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 socket system.^[4] Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.^[5]